1. Field of the Invention
The present disclosure relates to a moving picture encoding apparatus, and more particularly, to a moving picture encoding apparatus having an increased encoding speed, and a method thereof.
2. Description of the Related Art
In the MPEG-2, MPEG-4, and H.264 standards, an input image is divided into units of macroblocks, each having 16×16 pixels, which do not overlap, and motion estimation and compensation are performed in units of macroblocks. Discrete cosine transform and quantization are performed in units of blocks, each having 8×8 pixels. The input image is compressed by variable length coding the results.
A moving picture encoding apparatus using the MPEG-2, MPEG-4, and H.264 standards performs a decoding process, stores a decoded macroblock in a frame memory, and uses the decoded macroblock as a reference image for motion estimation when a subsequent image is encoded. An example of the moving picture encoding apparatus is disclosed in Japanese Patent Laid-Open Publication No. 1999-136680.
FIG. 1 is a block diagram of a conventional moving picture encoding apparatus 10. Referring to FIG. 1, the apparatus 10 includes a frame memory 12, an encoding unit 14, and an output buffer 16. The frame memory 12 is an input buffer, and an input image IN, which is a digital signal input from a camera system (not shown), is stored in the frame memory 12. The encoding unit 14 encodes the input image IN transmitted from the frame memory 12 in units of macroblocks. The output buffer 16 can be realized with a first-in first-out (FIFO) memory and outputs an image encoded by the encoding unit 14 as an output stream OUT.
The encoding unit 14 includes a motion estimation processor for calculating a motion vector by searching a previous image (or a previous frame) stored in an internal frame memory for a brightness block of 16×16 pixels most similar to a brightness block of a current macroblock of the input image IN, which is read from the frame memory 12. The motion estimation processor performs the most calculations (or operations) and the most frequent memory accesses in the moving picture encoding apparatus 10. The memory access is a read operation or a storage operation (write operation).
When the motion estimation processor performs motion estimation within a predetermined search range, a search area is necessary inside the frame memory included in the encoding unit 14. For example, when the search range is −16/+15 in a horizontal direction and a vertical direction, respectively, the search area is 48×48 pixels (brightness blocks of 9(=(16×2+16)×(16×2+16) pixels) macroblocks).
The 48×48 pixels are shown in FIG. 2, and indicated generally by the reference numeral 20. That is, FIG. 2 shows an example of image data stored in the search area of the frame memory included in the encoding unit 14 of FIG. 1. The search area data is stored in the frame memory included in the encoding unit 14 in a raster scan order and is also stored in a cache memory, e.g., SRAM, inside the motion estimation processor.
When the motion estimation processor performs motion estimation of the brightness block of the current macroblock, 16×48 new pixels must be read from the frame memory included in the encoding unit 14 since 32×48 pixels are stored in the cache memory included in the motion estimation processor. Here, a read time (or a read cycle) Tr required to read the pixels from the frame memory included in the encoding unit 14 is calculated by the following equation:Tr=(number of pixels per scan line/number of pixels per word+L)×number of total scan lines=(16/4+L)×48=48(4+L)
In the above equation, ‘word’ denotes a 4-byte read unit (or a data width), and L denotes predetermined latency, i.e., access latency when access is performed from a predetermined scan line to a subsequent scan line. The scan line corresponds to image data (pixels) consecutively stored in one page of the frame memory included in the encoding unit 14.
The access latency is generated when the frame memory included in the encoding unit 14 or the frame memory 12 is DRAM, synchronous DRAM (SDRAM), or double data rate (DDR) SDRAM. That is, access to the DRAM is performed in units of pages, and continuous image data read or write is possible in a selected page. However, when a page is changed, latency occurs.
When the motion estimation processor performs motion estimation of the brightness block of the current macroblock, the motion estimation processor must read the brightness block of the current macroblock from the frame memory 12. After encoding and decoding the read brightness block of the current macroblock, the decoded brightness block of the current macroblock is stored in the frame memory included in the encoding unit 14. Therefore, an access time Tc for accessing the frame memory 12 and the frame memory included in the encoding unit 14 is calculated by the following equation:Tc=(number of pixels per scan line/number of pixels per word+L)×number of scan lines per brightness block of a macroblock×access number=(16/4+L)×16×2=32(4+L)
In the above equation, ‘access number’ denotes a read and write number.
Therefore, a total memory access time Tt for the motion estimation of a brightness block of one current macroblock is calculated by the following equation:Tt=Tr+Tc=48(4+L)+32(4+L)=80L+320
Therefore, since a brightness block of each macroblock is read/stored from/in the frame memory 12 and the frame memory included in the encoding unit 14, which are DRAMs, each having the access latency L, in an order input from the camera system (the raster scan order), an encoding time of the conventional moving picture encoding apparatus shown in FIG. 1 can include a plurality of access latencies L. As a result, a moving picture encoding speed may decrease.